1. Field of the Invention
The present invention relates to a semiconductor read only memory, and more particularly to a semiconductor read only memory in which MOSFETs constituting memory cells are connected in parallel.
2. Description of the Prior Art
FIG. 5 shows an equivalent circuit of a semiconductor read only memory (hereinafter, sometimes referred to simply as "a ROM") which is conventionally and widely used. This ROM is a lateral ROM constructed in such a manner that memory cells 3 of MOSFETs are connected in parallel with respect to a plurality of bit lines 2 which cross word lines 1. It is known that each of the bit lines 2 is made of metal or made by diffusion (the former is referred to as a metal bit line, and the latter is referred to as a diffusion bit line).
In order to dispose memory cells more densely, a hierarchical system (hereinafter, referred to as a hierarchical bit line system) has been proposed (Japanese Patent Application No. 63-75300), as shown in FIG. 6. In the system, main bit lines Mb.sub.l, Mb.sub.l+1, . . . etc. and sub-bit lines bm.sub.2l, bm.sub.2l+1, . . . , etc. are hierarchically provided. In the hierarchical bit line system, each of the memory cells such as Mm.sub.2l.2 is connected between two adjacent sub-bit lines, and the memory cells are alternately assigned into two groups of odd-numbered banks such as Bm.sub.2l-1 and even-numbered banks such as Bm.sub.2l. For the selection of these banks, bank selecting MOSFETs QO.sub.m.2l, QE.sub.m.2l, . . . , etc. are provided on both ends of the sub-bit lines, respectively. Bank select lines BO.sub.m and BE.sub.m are connected to these bank selecting MOSFETs. The main bit lines Mb.sub.l, Mb.sub.l+1, . . . , etc. are connected to sense amplifiers such as SA.sub.l, or connected to GND via MOSFETs such as Q.sub.l+1.
In the ROM with the hierarchical bit line system, the wired pitch of the main bit lines can be made double as compared with the conventional lateral ROM shown in FIG. 5. The ROM with the hierarchical bit line system can advantageously reduce the parasitic capacitance on bit lines, and especially when the diffusion bit lines are used, the wiring resistance on bit lines can be greatly reduced.
However, when the diffusion bit lines are used in the hierarchical bit line system shown in FIG. 6, there arises a problem in that the diffusion resistance greatly varies depending on the position of a memory cell in a bank, which is described below, so that the value of discharge current for the read of information greatly varies depending on the position of the memory cell. There is another problem in that since the value of the diffusion resistance is large and the value of the discharge current is small, such a ROM is not suitable for high-speed reading.
For example, the case where information is read out from a memory cell Mm.sub.2l-1.1 by setting the bank select line BO.sub.m High, the other bank select line BE.sub.m Low, and the word line WL.sub.1 High is considered. In this case, the control signal VG for the transistor Q.sub.l (not shown) connected to the main bit line Mb.sub.l is made Low. The control signal VG for the transistor Q.sub.l-1 connected to the adjacent main bit line Mb.sub.l-1 is made High, so that the main bit line Mb.sub.l-1 is connected to the GND. The circuit in the above-mentioned state is shown in FIG. 7. The discharge current i flows through the main bit line Mb.sub.l, the bank selecting MOSFET QO.sub.m 2l-1, the sub-bit line b.sub.m.2l-1, the memory cell Mm.sub.2l-1.1, the sub-bit line b.sub.m.2l-2, and the main bit line Mb.sub.l-1, in this order. The total value of diffusion resistance of the sub-bit lines b.sub.m.2l-1 and b.sub.m.2l-2 in this path is 2r, if the resistance value between respective two cells is indicated by r.
Now, the case where information is read out from a memory cell Mm.sub.2l-1.n is considered. The circuit in this case is shown in FIG. 8. The total value of diffusion resistance of the sub-bit lines b.sub.m.2l-1 and b.sub.m.2l-2 in the path is 2nr. In this case, the diffusion resistance of sub-bit lines becomes largest.
As described above, in the ROM shown in FIG. 6, the value of diffusion resistance greatly varies depending on the position of a memory cell from which information is read out.